Hasil Pencarian  ::  Simpan CSV :: Kembali

Abstrak :
This book provides readers with a comprehensive review of the state of the art in error control for Network on Chip (NOC) links. Coverage includes detailed description of key issues in NOC error control faced by circuit and system designers, as well as practical error control techniques to minimize the impact of these errors on system performance.

Abstrak :
Networks-on-chip : from implementations to programming paradigms provides a thorough and bottom-up exploration of the whole NoC design space in a coherent and uniform fashion, from low-level router, buffer and topology implementations, to routing and flow control schemes, to co-optimizations of NoC and high-level programming paradigms. This textbook is intended for an advanced course on computer architecture, suitable for graduate students or senior undergrads who want to specialize in the area of computer architecture and Networks-on-Chip. It is also intended for practitioners in the industry in the area of microprocessor design, especially the many-core processor design with a network-on-chip. Graduates can learn many practical and theoretical lessons from this course, and also can be motivated to delve further into the ideas and designs proposed in this book. Industrial engineers can refer to this book to make practical tradeoffs as well. Graduates and engineers who focus on off-chip network design can also refer to this book to achieve deadlock-free routing algorithm designs.

Abstrak :
This book presents an overview of the issues related to the test, diagnosis and fault-tolerance of Network on Chip-based systems. It is the first book dedicated to the quality aspects of NoC-based systems and will serve as an invaluable reference to the problems, challenges, solutions, and trade-offs related to designing and implementing state-of-the-art, on-chip communication architectures.

Abstrak :
ABSTRAK
Saat ini, Named Data Networking NDN telah menjadi solusi terobosan dan pilihan potensial untuk arsitektur Internet generasi berikutnya. Sebelum NDN akan merilis atau menguji ke pasar, akan lebih baik untuk meninjau aspek keamanan. Menurut arsitektur NDN dan alur kerja, NDN memiliki kemungkinan berada dalam situasi diserang melawan serangan DoS/DDoS. Serangan DoS/DDoS pada NDN selanjutnya dikenal dengan istilah Interest Flooding Attack IFA . Pending Interest Table bisa menjadi pintu masuk IFA pada kasus ini. Banyak paper yang menawarkan sejumlah metode mitigasi terhadap IFA. Tesis ini bertujuan untuk menemukenali metode yang dapat digunakan pada kondisi riil melalui simulasi pada topologi Rocketfuel dengan melakukan berbagai skenario pengujian seperti variasi nilai data payload, nilai round-trip time, dan lamanya waktu serangan. Data payload yang diujikan variative mulai dari yang berukuran 400 bytes, 700 bytes, 1100 bytes, 1500 bytes, dan 2000 bytes. Ada tiga metode mitigasi yang diujikan pada tesis ini yakni Satisfaction Pushback, Satisfaction Accept, dan Token Bucket with per Interface Fairness. Pengujian dilakukan menggunakan NDNSim versi 1.0 yang telah di custom. Hasil akhirnya Satisfaction Pushback merupakan metode mitigasi terbaik dibandingkan Satisfaction Accept dan Token Bucket with per Interface Fairness. Kemampuan metode mitigasi Satisfaction Pushback dalam memastikan Consumer mendapatkan layanan yang diinginkan dari Produser berkisar antara 63 - 85,8 . Interest Satisfaction Ratio ISR dicapai saat serangan terjadi dalam 600 detik dengan nilai round-trip time sebesar 150 ms dan data payload sebesar 2000 byte. ISR tertinggi dicapai saat serangan terjadi dalam 300 detik dengan nilai round-trip time sebesar 500 ms dan ukuran data payload sebesar 2000 byte.

---

ABSTRACT
Currently, Named Data Networking NDN has become a breakthrough solution and a potential choice for next generation Internet architecture. Before NDN can be released into the market, it would be better to review its security aspect. According to the NDN architecture and workflow, NDN has the possibility of being in a situation of being attacked against a Denial of Service DoS Distributed Denial of Services DDoS . DoS DDoS attack on NDN is known as an Interest Flooding Attack IFA . Pending Interest Table could be the entrance of IFA in this case. This thesis aims to identify methods that can be used in real conditions through simulation of Rocketfuel topologies by performing various test scenarios such as variations of payload data values, round trip time values, and length of attack time. The payload data tested is varied from 400, 700, 1100, 1500, and 2000 bytes. There are three mitigation methods tested on this works namely Satisfaction Pushback, Satisfaction Accept, and Token Bucket with per Interface Fairness. Testing is done using NDNSim version 1.0 which has been customized. The end result is Satisfaction Pushback is the best mitigation method than Satisfaction Accept and Token Bucket with per Interface Fairness. While attacks occurred, satisfaction pushback mitigation method is capable in ensuring consumer to get the desired service ranges between 63 85,8 . The lowest interest satisfaction ratio ISR achieved while attacks occurred in 600 seconds with round trip time value on 150 ms and data payload size 2000 bytes. The highest ISR achieved while attacks occurred in 300 seconds with round trip time value on 500 ms and data payload size 2000 bytes.

Abstrak :
This book provides a comprehensive survey of recent progress in the design and implementation of Networks-on-Chip. It addresses a wide spectrum of on-chip communication problems, ranging from physical, network, to application layers. Specific topics that are explored in detail include packet routing, resource arbitration, error control/correction, application mapping, and communication scheduling. Additionally, a novel bi-directional communication channel NoC (BiNoC) architecture is described, with detailed explanation.

Abstrak :
This book describes a flexible and largely automated methodology for adding the estimation of power consumption to high level simulations at the electronic system level (ESL). This method enables the inclusion of power consumption considerations from the very start of a design. This ability can help designers of electronic systems to create devices with low power consumption. The authors also demonstrate the implementation of the method, using the popular ESL language “SystemC”. This implementation enables most existing SystemC ESL simulations for power estimation with very little manual work. Extensive case-studies of a Network on Chip communication architecture and a dual-core application processor “ARM Cortex-A9” showcase the applicability and accuracy of the method to different types of electronic devices. The evaluation compares various trade-offs regarding amount of manual work, types of ESL models, achieved estimation accuracy and impact on the simulation speed. - Describes a flexible and largely automated ESL power estimation method; - Shows implementation of power estimation methodology in SystemC; - Uses two extensive case studies to demonstrate method introduced.

Abstrak :
This book addresses reliability and energy efficiency of on-chip networks using cooperative error control. It describes an efficient way to construct an adaptive error control codec capable of tracking noise conditions and adjusting the error correction strength at runtime. Methods are also presented to tackle joint transient and permanent error correction, exploiting the redundant resources already available on-chip. A parallel and flexible network simulator is also introduced, which facilitates examining the impact of various error control methods on network-on-chip performance.