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Abstrak :
Area parkir tertutup merupakan salah satu tempat terjadinya polusi udara tertutup akibat emisi gas buang kendaraan bermotor yang tidak dapat keluar dari ruangan tertutup. Polusi udara tertutup jauh lebih berbahaya dibandingkan dengan polusi udara terbuka. Skripsi ini merancang, membuat prototipe, serta menganalisis sistem peringatan polusi udara menggunakan Field Programmable Gate Array (FPGA) Xilinx Spartan 3E. Peralatan yang digunakan sebagai sistem peringatan dalam prototipe berupa LED, buzzer, dan fan. Metode yang digunakan dalam sistem embedded ini mengikuti Software Development Life Cycle (SDLC). Bahasa yang digunakan adalah VHDL dengan software Xilinx ISE. Berdasarkan hasil uji coba, didapatkan hasil bahwa timing diagram antara simulasi Register Transfer Level (RTL) dan implementasi tidak jauh berbeda dengan selisih waktu 0.37%, sehingga untuk melihat output dan response time keseluruhan sistem dapat melalui simulasi RTL. Waktu yang dibutuhkan sistem untuk mengeluarkan CO lebih lama 60-71% dari perhitungan dikarenakan terdapat jeda waktu pembacaan kadar CO oleh sensor. Diperlukan sebanyak 1024 sampel data ADC pada FPGA Spartan 3E agar hasil pembacaan sensor stabil. ......Closed parking area can deposit motor gas emission that could be harmful to humans. Indoor air pollution is more dangerous than the outdoor one. This thesis discusses the design, prototype making, and analyzes the embedded air pollution warning system using Field Programmable Gate Array (FPGA) Xilinx Spartan 3E. Other equipments use in this system are LED, buzzer, and fan. The method used in this research follows the Software Development Life Cycle (SDLC). The programming language used in configuring the FPGA Xilinx Spartan 3E is VDHL using Xilinx ISE Design Suite 13.2. Based on result, Register Transfer Level (RTL) simulation and implementation timing diagram does not have much different with a difference 0,37% so to see the output and overall system response time can be through RTL simulation. Time required to remove carbon monoxide from the dummy box is 60-71% longer than the calculation because there is a lag time of the reading levels of CO by the sensor. 1024 data ADC samples are needed in order to give a stable result from FPGA Spartan 3E.

Abstrak :
Penulis telah membuat sebuah alat Penghitung jumlah pengunjung dalam suatu ruangan yang dilakukan secara otomatis berbasis FPGA. Dimana pada alat ini kita mempergunakan sensor LDR sebagai komponen untuk mendeteksi pengunjung yang lewat dan keypad digunakan sebagai komponen untuk menginput jumlah kapasitas dalam suatu ruangan. Pada alat ini menggunakan menggunakan FPGA sebagai proses pengendali untuk menghitung serta buzzer sebagai penanda bahwa kapasitas telah penuh dari suatu ruangan. Implementasi dari alat ini adalah mampu melakukan perhitungan baik penambahan maupun pengurangan. Hasil perhitungan ditampilkan kedalam layar LCD. Bahasa pemograman yang dipakai dalam kendali FPGA adalah VHDL. Dalam pemograman dibagi menjadi dua yaitu program utama dan subprogram. Proram utama sebagai fungsi pengendali sedangkan pada subprogram sebagai fungsi tampilan ke layar LCD. Percobaan menunjukkan bahwa semua sistem berfungsi untuk digunakan dengan benar. ......Author designs automatic counters that counts number of visitors in a room. The device is develop based on FPGA. The tools used are LDR as a sensor for detecting passing visitors and keypad as components to set the maximum capacity of a room. Buzzer is used as the output device to signal audience that the room are full with visitor. The implementation of this tool is capable of performing the calculations for both the addition and subtraction. The calculation result is displayed into the LCD screen. VHDL is programming language used to the control FPGA. The programming is divided into two: main programs and sub programs. The main program as a fuction of controller while the sub program as a fuction of the display to the LCD screen. The experiment shows that all to function systems used correctly.

Abstrak :
ABSTRACT
Proyek ini adalah bagian dari suatu proyek besar yang dikembangkan oleh grup riset Communications Num riques COMNUM di Departement of Opto Acousto Electronique DOAE pada Institut d 39 Electronique de Micro lectronique et de Nanotechnologie IEMN Valenciennes France Proyek tersebut berkonsentrasi pada pengembangan sistem komunikasi bergerak dengan konsumsi energi yang rendah Pada paper ini mengemukakan penggunaan UWB Ultra Wide Band sebagai dasar pulsa sinyal untuk telekomunikasi Sinyal tersebut akan dibangkitkan dengan menggunakan teknik modulasi baru yang disebut OAM Orthogonal Amplitude Modulation Potensi keunggulan dari transmisi UWB adalah rendah energy rate tinggi tahan terhadap multipath propagasi hardware transceiver yang tidak compleks dan interferensi yang rendah Potensi tersebut akan digabungkan dengan keunggulan FPGA Field Programmable Gate Array yang memiliki kecepatan transfer data tinggi integrasi pada level yang tinggi fleksibilitas tinggi dan biaya pengembangan yang rendah Sistem ini akan berjalan pada ranah simulasi dan sistem asli pada peralatan perangkat keras Kartu FPGA yang digunakan adalah ADM XRC 5T1 yang berbasiskan Xilinx Virtex 5 dan akan digabungkan dengan kartu DAC Digital to Analog Conveter XRM DAC D4 1G Kita akan melihat bahwa implementasi UWB dengan modulasi OAM pada FPGA akan berjalan dengan baik pada simulasi akan tetapi untuk dapat berjalan dengan baik pada sistem asli butuh beberapa adaptasi dan eksperimen Tidak mengherankan bahwa implementasi sistem asli pada FPGA jauh lebih kompleks daripada simulasi berdasarkan perangkat lunak

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ABSTRACT
This Project is the part of a big project that has been developed by research group Communications Numériques (COMNUM) in the Departement of Opto-Acousto-Electronique (DOAE) at the Institut d'Electronique de Microélectronique et de Nanotechnologie (IEMN) Valenciennes, France. The project concerns is the development of high mobility communication with low power energy consumption. This paper proposes the utilization of UWB (Ultra Wide Band) as the basic signal pulse for telecommunication. It will be generated with new technique of modulation OAM (Orthogonal Amplitude Modulation). The potential advantages of UWB transmissions such as low power, high rate, immunity to multipath propagation, less complex transceiver hardware, and low interference, will be combined with the superiority of FPGA (Field Programmable Gate Array) which provides high speed, high level of integration, high flexibility, and low development costs. The system will be running in the simulation field and in the real system on the hardware equipment. The FPGA card is ADM-XRC-5T1 based on Xilinx Virtex 5, merged with DAC (Digital to Analog Converter) card XRM-DAC-D4/1G. We will see that implementation of UWB with modulation OAM on FPGA will be running well in simulation, but for implementation in real system we should make several adaptation and experiment. No wonder that the real system implementation in FPGA are much more complicated and different with the simulation base on software.

Abstrak :
This thesis discusses about the implementation of an Ultra Wide Band (UWB) communication system based on the FPGA (Field Programmable Gate Array) using the Orthogonal Amplitude Modulation (OAM) which is the newer modulation technique that can provide a higher speed of data transmission rate. The OAM (Orthogonal Amplitude Modulation) is the combination between the Bi-Phase Modulation (BPM) and Pulse Position Modulation (PPM) using the orthogonal signal. The work is focus on the ADC data captured, performing parallel correlation, synchronization and decoding process. The basic principle of the system is: the transmitted signal is first coded into the symbols by using 4- OAM. Then, this data are transmitted by a UWB antenna. The UWB antenna on the receiver side receives these signals and captured by a high speed ADC and results 16 data samples in parallel on every FPGA clock cycle. These signal are performed the parallel correlation with the reference signal which is stored in the FPGA memory. The results of correlation then can be decoded by firstly finding the peak of correlation result which is refers to the received symbol. By using the PCI express communication, the decoded data is transferred to the host application as a valid data received.

Abstrak :
Pada penelitian ini diterapkan algoritma kriptografi Trivium pada perangkat keras FPGA DE0-Nano yang terhubung ke komputer menggunakan komunikasi data serial melalui USB to UART TTL converter. Data yang dienkripsi dikirimkan melalui komputer dan setelah proses enkripsi berakhir dikirimkan kembali dengan menggunakan bantuan aplikasi serial port terminal. Penelitian ini bersifat kualitatif yang merujuk pada keberhasilan pencapaian sistem kriptografi dan perbandingan keefisienan waktu proses kriptografi dengan penggunaan perangkat lunak. Hasil penelitian menunjukkan bahwa algoritma kriptografi Trivium berhasil diterapkan dalam FPGA DE0-Nano untuk mengenkripsi dan mendekripsi berbagai jenis berkas dengan waktu yang lebih sedikit untuk proses kriptografi jika dibandingkan dengan penggunaan perangkat lunak. ......This study focused with designing and implementation of Trivium as cryptography algorithm in hardware device DE0 Nano board FPGA which connected to computer using serial data communication by a USB to UART TTL converter. Data or file that will be encypt transmitt from computer and after encryption process has finished, it will be loopback. Transmitt and receive process used a serial port terminal software. This study is qualitative, that is based on sistem succsessfull implemented as cryptography system and compare time eficiency on cryptography process to other system using software. The result of this study show that Trivium cryptography algorithm has been successfull implemented on FPGA DE0 Nano to encrypt and decrypt various type of file and need less time for cryptography process than using software.

Abstrak :
This is not a book on algorithms. It is a book that shows how to translate efficiently an algorithm to a circuit, using techniques such as parallelism, pipeline, loop unrolling, and others. Numerous examples of FPGA implementation are described throughout this book and the circuits are modeled in VHDL. Complete and synthesizable source files are available for download.

Abstrak :
Penerapan sistem embedded yang praktis dan portable menjadi salah satu tantangan saat ini. FPGA menawarkan perancangan sistem yang hemat daya, cepat, dan mudah dalam pengembangan lanjutan. Perancangan sistem cepat komunikasi secara serial dengan bluetooth low energy BLE pada FPGA dapat meningkatkan fleksibilitas, efisiensi daya, dan performa. Sistem komunikasi serial dengan metode UART akan diimplementasikan pada FPGA Xilinx Zynq-7000. FPGA akan diintegrasikan dengan Bluetooth low energy HM-10 dengan metode UART pada nilai baudrate yang tinggi. Enkripsi AES juga akan diimplementasikan pada FPGA dan diharapkan dapat menjamin aspek keamanan data. Pengujian sistem ini menunjukkan bahwa penggunaan baudrate yang tinggi pada bluetooth, selain dipengaruhi oleh latensi, dapat mempercepat transmisi data. Integrasi antara FPGA dengan Bluetooth low enery diharapkan mampu menjadi salah satu alternatif pengembangan sistem embedded yang efisien, mudah digunakan, dan praktis dengan komunikasi secara nirkabel. ......Implementation of an easy to use and portable embedded system is one of the challenges today. FPGA offers system design that is power efficient, fast, and easy in advanced development. Design of fast serial communication systems with low energy bluetooth BLE on FPGAs can improve flexibility, power efficiency, and performance. Serial communication system with UART method will be implemented on Xilinx Zynq 7000 FPGA. FPGA will be integrated with Bluetooth low energy HM 10 with UART method at high baudrate value. AES encryption will also be implemented on the FPGA and to ensure data security aspects. Result of this system shows that the use of high baudrate on bluetooth, besides influenced by latency, can speed up data transmission over bluetooth. Integration between FPGA and Bluetooth low enery can be an alternative to develop power efficient, easy to use, and flexible embedded system with wireless communication.

Abstrak :
This book presents a new FPGA architecture known as tree-based FPGA architecture, due to its hierarchical nature. This type of architecture has been relatively unexplored despite their better performance and predictable routing behavior, as compared to mesh-based FPGA architectures. In this book, we explore and optimize the tree-based architecture and we evaluate it by comparing it to equivalent mesh-based FPGA architectures.

Abstrak :
This book suggests and describes a number of fast parallel circuits for data/vector processing using FPGA-based hardware accelerators. Three primary areas are covered: searching, sorting, and counting in combinational and iterative networks. These include the application of traditional structures that rely on comparators/swappers as well as alternative networks with a variety of core elements such as adders, logical gates, and look-up tables. The iterative technique discussed in the book enables the sequential reuse of relatively large combinational blocks that execute many parallel operations with small propagation delays. For each type of network discussed, the main focus is on the step-by-step development of the architectures proposed from initial concepts to synthesizable hardware description language specifications. Each type of network is taken through several stages, including modeling the desired functionality in software, the retrieval and automatic conversion of key functions, leading to specifications for optimized hardware modules. The resulting specifications are then synthesized, implemented, and tested in FPGAs using commercial design environments and prototyping boards. The methods proposed can be used in a range of data processing applications, including traditional sorting, the extraction of maximum and minimum subsets from large data sets, communication-time data processing, finding frequently occurring items in a set, and Hamming weight/distance counters/comparators. The book is intended to be a valuable support material for university and industrial engineering courses that involve FPGA-based circuit and system design.