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"This book is intended as a system engineer's compendium, explaining the dependencies and technical interactions between the onboard computer hardware, the onboard software and the spacecraft operations from ground. After a brief introduction on the subsequent development in all three fields over the spacecraft engineering phases each of the main topis is treated in depth in a separate part."

"Contents :- Foreword - The Microelectronics Desk Reference - System Level Failure Analysis Process: Making Failure Analysis a Value Add Proposition in today’s High Speed Low Cost PC environment - Board Level Failure Mechanisms and Analysis in Hand-held Electronic Products - Failure Analysis Flow for Package Failures - Wafer Level Failure Analysis Process Flow - Flip-Chip and “Backside” Sample Preparation Techniques - Failure Analysis in a Fabless/Outsourced World - Circuit Edit at First Silicon - The Process of Editing Circuits Through the Bulk Silicon - Curve Tracer Data Interpretation for Failure Analysis - A Primer on Simple Device Problems and Curve Tracer Characteristics - Electronics and Failure Analysis - Analog Device and Circuit Characterization - IC Testing: Background, Directions and Opportunities for Failure Analysis - Using Scan Based Techniques for Fault Isolation in Logic Devices - The Power of Semiconductor Memory Failure Signature Analysis - Common Defects Encountered During Semiconductor Manufacturing - System Level Board Fabrication and Assembly Process Anomalies and Associated Failures Categories - Characterization of Anomalies in Flip-Chip Solder Joins in Ceramic Packaging - Identification of Latent Defects in Advanced Glass Ceramic MCM Packaging - Electrostatic Discharge (ESD) and Latchup Failures in Advanced CMOS Technologies - Electrical and Optical Characterization of Latchup - Failure Analysis of Microelectromechanical Systems (MEMS) - Failure Analysis of Passive Components - Failure Analysis and Reliability of Optoelectronic Devices - Die-level Fault Localization with X-ray Microscopy - X-ray Microtomography Tools for Advanced IC Packaging Failure Analysis - Acoustic Microscopy of Semiconductor Packages - Electronic Package Fault Isolation Using TDR - Current Imaging using Magnetic Field Sensors - Chip access techniques - Low Stress FA Sample Preparation of Flip Chip Devices with Low-K Dielectric Interconnect Layers - Plastic BGA Module FA Process Flow Development - Chip-Scale Packages and Their Failure Analysis Challenges - Backside Analysis Using Re-Package Techniques - Photon Emission Microscopy - Fundamentals of Photon Emission (PEM) in Silicon – Electroluminescence for Analysis of Electronic Circuit and Device Functionality - Picosecond Imaging Circuit Analysis – PICA - Thermal Defect Detection Techniques - Thermal Failure Analysis by IR Lock-in Thermography - Beam-Based Defect Localization Methods - Principles of Thermal Laser Stimulation Techniques - Introduction to Laser Voltage Probing (LVP) of Integrated Circuits - SEM and FIB Passive Voltage Contrast - Electron Beam Probing - Delayerimg Techniques: Dry Processes Wet Chemical Processing and Parallel Lapping - Plasma Delayering of Integrated Circuits - The Art of Cross Sectioning - Delineation Etching of Semiconductor Cross Sections - Special Techniques for Backside Deprocessing - Deprocessing Techniques for Copper, Low K, and Soi Devices - PCB SMT Solder Joint Failure Analysis - Improved Methodologies for Identifying Root-Cause of Printed Board Failures - Optical Microscopy - Scanning Electron Microscopy - Ultra-high Resolution in the Scanning Electron Microscope - Focused Ion Beam (FIB) Systems: A Brief Overview - Transmission Electron Microscopy for Failure Analysis of Integrated Circuits - Atomic Force Microscopy: Modes and Analytical Techniques with Scanning Probe Microscopy - Energy Dispersive X-ray Analysis - Analysis of Submicron Defects by Auger Electron Spectroscopy (AES) - SIMS Solutions for Next Generation IC Processes and Devices - Submicron CMOS Devices - Reliability and Quality Concepts for Failure Analysts - CAD Navigation in FA and Design/Test Data for Fast Fault Isolation - Best of the EDFAS Email Discussion Forum 2000-2004 - Failure Analysis Roadmaps - Assembly Analytical Forum Analytical Tool Roadmap ISTFA 2003 Rev 0 White Paper - Education and Training for the Analyst - Managing the Unpredictable – A Business Model for Failure Analysis Service - Management Principles and Practices for the Failure Analysis Laboratory - Failure Analysis Terms and Definitions - JEDEC Standards for Failure Analysis - Education/Training Sources and References - ISTFA Subject Index "

"Contents :- Microelectronics failure analysis desk reference, 2001 supplement - Preface - Microelectronic Failure Analysis Desk Reference 2001 Supplement - FIB Backside Isolation Techniques - The SEM Lab, From Laboratory Logistics to Final Sample Preparation Techniques for SEM Analysis of Semiconductors - Cross Sectioning with a Pivoting Sample Block - Focused Ion Beam Cross Sectioning as a Compliment or an Alternative to Conventional Mechanical Sectioning Techniques - Alternatives to Cross-Sectional Simple Preparation for Package and Board-Level Failure Analysis - Automation To Boost Productivity And Increase Repeatability: (A Sampling of Available Tools and Vendors) - Multi-Functional, Semi-Automatic Sample Preparation for Failure Analysis - SMPT©-Sub-Micron Polishing Technology For Automated Sample Preparation - Automated Techniques For SEM And TEM Sample Preparation - Sample Preparation Techniques for Site-Specific Cross-Sectional Analysis of High-Aspect-Ratio FIB Repair Sites - Deprocessing, Cross-Sectioning and FIB Circuit Modification of Parts Having Copper Metallization - Scanning Capacitance Microscopy of Junction and Non-Junction Samples - Electrical Probing of Deep Sub-Micron Integrated Circuits Using Scanning Probe Techniques - Application of Tunneling Atomic Force Microscopy (TUNA) to Failure Analysis - GoFATA: Glossary of Failure Analysis Tool Acronyms - ISTFA Subject Index "

"Contents - IPFA 2000 Best Paper Award Winner - Application of Focused Ion Beam System as a Defect Localization and Root Cause Analysis Tool - Session 1: Advanced Techniques 1 - X-Ray Tomography of Integrated Circuit Interconnects: Past and Future - X-ray Nanotomog Raphy (XRMT) Tool for Non-Destructive High-Resolution Imaging of ICs - Single Point PICA Probing with an Avalanche Photo-Diode - Session 2: Advanced Techniques 2 - Comparison of Laser and Emission Based Optical Probe Techniques - Resistive Interconnection Localization - Optical Waveform Probing–Strategies for Non-Flipchip Devices and Other Applications - Advanced LIVA/TIVA Techniques - Session 3: Packaging - Super-conducting Quantum Interference Device Technique: 3-D Localization of a Short Within a Flip Chip Assembly - Integration of SQUID Microscopy into FA Flow - Evaluation of alternative Preparation Methods for Failure Analysis at modern Chip-and Package Technologies - TDR Analysis of Advanced Microprocessors - Signal Trace and Power Plane Shorts Fault Isolation Using TDR - Session 4: Poster Session - Backside Etch: A New FA Technique for Gate Oxide Pinhole and Si Defect Identification for Power IC Devices - Fabrication Of Inexpensive Decapsulation Fixtures for Small or Unique Plastic Packages - Failure Analysis of Plasma-Induced Submicron CMOS IC Yield Loss by Backside Photoemission Microscopy - Failure Types & Analysis In Cu Process Development of Design-Rule 0.18 μm CPU - TEM Examination of a Specified Site Identified by X-SEM in Microelectronics Failure Analysis - Design Debug and Design Fix Verification in a Failure Analysis Lab for a RF/IF Circuit for Cellular Applications With High Battery Save and Electrostatic Discharge Leakage: A Case Study - Self Aligned Contact Wordline-Bitline Shorts in Memory ICs–a Comparative Study of a Failure Mode, Its Root Causes, And Simple, But Highly Effective Analysis Techniques - A Spatial Filtering Localisation Tool for Failure Analysis of Periodic Circuits - New Manifestation of Electrical Overstress in Advanced Device Technologies - Session 5: Backside 1 - Implementing Thermal Laser Stimulation in a Failure Analysis Laboratory - Calibration Technique for MCT FPA used for Backside Emission Microsopy - Liquid Immersion Objective for High-Resolution Optical Probing of Advanced Microprocessors - New Signal Detection Methods for Thermal Beam Induced Phenomenon - CNC Milling and Polishing Techniques for Backside Sample Preparation - Session 6: SPM - Characterization of MOS Devices by Scanning Thermal Microscopy (SThM) - Contactless Failure Analysis of Integrated Circuits Via Current Contrast Imaging with Magnetic Force Microscopy - Multiple Probe Deep Sub-Micron Electrical Measurements Using Leading Edge Micro-Machined Scanning Probes - Electrical Characterization of Circuits with Low K Dielectric Films and Copper Interconnects - Session 7: Backside 2 - Emission Microscopy and Thermal Laser Stimulation for Backside Failure Localization - CMOS Front-End Investigation over Large Areas by Deprocessing from the Back Side - New Techniques for the Identification of Defects in Multi-Layer Flip-Chip Packages - Session 8: Case Histories 1 - Board Level Failure Analysis of Chip Scale Packages - IC Failure by Electrical Overstress (EOS) - The Search for the Elusive EOS Monster - Session 9: FIB - Effect of Ga Staining due to FIB Editing on IR Imaging of Flip Chips - Water Vapor Enhancement for Elemental Analysis Using Focused Ion Beam Secondary Ion Mass Spectrometry (FIB-SIMS) - Various Focused Ion Beam Microsurgery Techniques in Dealing with Copper Metalization in ICs - Reliability of Bipolar and MOS Circuits After FIB Modification - Mass Production Cross-Section Tem Samples by Focus Ion Beam Masking and Reactive Ion Etching - Session 10: Case Histories 2 - A Successful Failure Analysis Using Front and Backside Fault Localization Techniques on a Deep Sub-Micron CMOS Device - Use of STEM in Nanometer Level Defect Analysis of SRAM Devices - A New Deprocessing Technique By Selective Wet-Etch Of Passivation And Inter Metal Dielectric Layers For Submicron Devices - SRAM Failure Analysis Flow - Physical Failure Analysis on Vertical Dielectric Films - Session 11: MEMS - Design for Reliability of MEMS/MOEMS for Lightwave Telecommunications - Mechanical Characterization of Materials Used in MEMS - Optical Imaging of High-Frequency Resonances and Semi-Static Deformations in Micro-Elec"

"Contents : - Foreword - The Microelectronics Desk Reference - System Level Failure Analysis Process: Making Failure Analysis a Value Add Proposition in today’s High Speed Low Cost PC environment - Board Level Failure Mechanisms and Analysis in Hand-held Electronic Products - Failure Analysis Flow for Package Failures - Wafer Level Failure Analysis Process Flow - Flip-Chip and “Backside” Sample Preparation Techniques - Failure Analysis in a Fabless/Outsourced World - Circuit Edit at First Silicon - The Process of Editing Circuits Through the Bulk Silicon - Curve Tracer Data Interpretation for Failure Analysis - A Primer on Simple Device Problems and Curve Tracer Characteristics - Electronics and Failure Analysis - Analog Device and Circuit Characterization - IC Testing: Background, Directions and Opportunities for Failure Analysis - Using Scan Based Techniques for Fault Isolation in Logic Devices - The Power of Semiconductor Memory Failure Signature Analysis - Common Defects Encountered During Semiconductor Manufacturing - System Level Board Fabrication and Assembly Process Anomalies and Associated Failures Categories - Characterization of Anomalies in Flip-Chip Solder Joins in Ceramic Packaging - Identification of Latent Defects in Advanced Glass Ceramic MCM Packaging 181 Electrostatic Discharge (ESD) and Latchup Failures in Advanced CMOS Technologies - Electrical and Optical Characterization of Latchup - Failure Analysis of Microelectromechanical Systems (MEMS) - Failure Analysis of Passive Components - Failure Analysis and Reliability of Optoelectronic Devices - Die-level Fault Localization with X-ray Microscopy - X-ray Microtomography Tools for Advanced IC Packaging Failure Analysis - Acoustic Microscopy of Semiconductor Packages - Electronic Package Fault Isolation Using TDR - Current Imaging using Magnetic Field Sensors - Chip access techniques - Low Stress FA Sample Preparation of Flip Chip Devices with Low-K Dielectric Interconnect Layers - Plastic BGA Module FA Process Flow Development - Chip-Scale Packages and Their Failure Analysis Challenges - Backside Analysis Using Re-Package Techniques - Photon Emission Microscopy - Fundamentals of Photon Emission (PEM) in Silicon – Electroluminescence for Analysis of Electronic Circuit and Device Functionality - Picosecond Imaging Circuit Analysis – PICA - Thermal Defect Detection Techniques - Thermal Failure Analysis by IR Lock-in Thermography - Beam-Based Defect Localization Methods - Principles of Thermal Laser Stimulation Techniques - Introduction to Laser Voltage Probing (LVP) of Integrated Circuits - SEM and FIB Passive Voltage Contrast - Electron Beam Probing - Delayerimg Techniques: Dry Processes Wet Chemical Processing and Parallel Lapping - Plasma Delayering of Integrated Circuits - The Art of Cross Sectioning - Delineation Etching of Semiconductor Cross Sections - Special Techniques for Backside Deprocessing - Deprocessing Techniques for Copper, Low K, and Soi Devices - PCB SMT Solder Joint Failure Analysis - Improved Methodologies for Identifying Root-Cause of Printed Board Failures - Optical Microscopy - Scanning Electron Microscopy - Ultra-high Resolution in the Scanning Electron Microscope - Focused Ion Beam (FIB) Systems: A Brief Overview - Transmission Electron Microscopy for Failure Analysis of Integrated Circuits - Atomic Force Microscopy: Modes and Analytical Techniques with Scanning Probe Microscopy - Energy Dispersive X-ray Analysis - Analysis of Submicron Defects by Auger Electron Spectroscopy (AES) - SIMS Solutions for Next Generation IC Processes and Devices - Submicron CMOS Devices - Reliability and Quality Concepts for Failure Analysts - CAD Navigation in FA and Design/Test Data for Fast Fault Isolation - Best of the EDFAS Email Discussion Forum 2000-2004 - Failure Analysis Roadmaps - Assembly Analytical Forum Analytical Tool Roadmap ISTFA 2003 Rev 0 White Paper - Education and Training for the Analyst - Managing the Unpredictable – A Business Model for Failure Analysis Service - Management Principles and Practices for the Failure Analysis Laboratory - Failure Analysis Terms and Definitions - JEDEC Standards for Failure Analysis - Education/Training Sources and References - ISTFA Subject Index "

"Contents :- IPFA 2002 Best Paper Award Winner - SEM/SThM-Hybrid-System: A New Tool for Advanced Thermal Analysis of Electronic Devices - From Microns to Molecules–Can FA Remain Viable Through the Next Decade? - Soft Defect Localization (SDL) on ICs - Fault Localization and Functional Testing of ICs by Lock-in Thermography - Visualisation of Electrically Active Areas Using Electron Holography - A Study of Photoelectron Emission Microscopy Contrast Mechanisms Relevant to Microelectronics - Application of Acoustic Fourier Domain Imaging for the Evaluation of Advanced Micro Electronic Packages - Orientation Imaging Microscopy Applications in Cu-Interconnects and Cu-Cu Wire Bonding - Materials Analysis and Process Monitoring in MegaFabs - STEM (Scanning Transmission Electron Microscopy) in a SEM (Scanning Electron Microscope) for Failure Analysis and Metrology - Microcalorimeter Energy Dispersive X-Ray Spectroscopy in Routine Semiconductor Failure Analysis - A Working Method for Adapting the (SEM) Scanning Electron Microscope to Produce (STEM) Scanning Transmission Electron Microscope Images - Applications of EELS to Semiconductor Devices Failure Analysis by Using a 300 keV TEM - Laser Milling Methods for Package Failure Analysis - Laser Decapsulation of Transfer Molded Plastic Packages for Failure Analysis - Investigation of Microstructure Change on Ni-based UBM Systems in Lead Free Solder - Failure Analysis Strategy For 2 Stacked Die CSP - Evaluation of Package Defects by Thermal Imaging Techniques - Backside Hot Spot Detection - Optimizing Backside Image Quality - Infrared Microthermography for Integrated Circuit Fault Location; Sensitivity and Limitations - Failure Analysis of Tungsten Contact Failure in a 0.13 um CMOS Process - Backside Photoemission and Infrared Microthermography for Rapid Debug of Compound Semiconductor Devices - Laser-Voltage-Prober Measurements on Bipolar Devices - Application of Focused Ion Beam in Debug and Characterization of 0.13 um Copper Interconnect Technology - Thin-Die Flip Chip Physical-FA Process Flow - Failure Mechanism and Rootcause Analysis of UBGA Solder Ball Contamination - Passivation Damage and Residue-Induced Package Failure Analysis For a 16 Lead SOIC GaAs RF/IF Package - Study on a Single NFET Degradation After Circuit Modification with FIB - New Techniques to Improve the Efficiency of TEM Sample Preparation - A Transmission X-Ray Microscope (TXM) for Non-Destructive 3D Imaging of ICs at Sub-100 nm Resolution - A Broadband Model for Ultrasonic Pulses in the Presence of Thin Layers in Microelectronics - Beam-Based Localization Techniques for 0.18 um IC Failure Analysis after Reliability Test - Methodologies for Isolating Faults in Multi Chip Fiber Optic Transceivers that Use GHz Mixed Signal ICs - Application of Various Fault Localization Techniques to Different Types of 6T- SRAM column Failures - Missing Metal Pillar Failure Analysis-A Plug Technology Issue - Reliability and failure analysis of RF MEMS switches - Failure Analysis of Polysilicon Micromirror Arrays - Failure Analysis of the Digital Micromirror Device - Wavefront Coded Imaging Systems for MEMS Analysis - Sample preparation for Vertical Transistors in DRAM - A Methodology to Reduce Ion Beam Induced Damage in TEM Specimens Prepared by FIB - CMOS Backside Deprocessing With TMAH/IPA as a Sample Preparation Procedure for Failure Analysis - Investigation of Choline Hydroxide for Selective Silicon Etch from a Gate Oxide Failure Analysis Standpoint - In situ Decapsulation of Plastic Encapsulated Devices Mounted to a Printed Circuit Board - A Standardized Scientific Method Formulation for Failure Analysis Application - Probeless FA Approach: a Breakthrough Simulation Based Failure Analysis Method - Electrical Faults Captured by In-Line E-beam Inspection and Failure Analysis - Effect of Corner Underfill Voids on Chip Scale Package (CSP) Performance Under Mechanical Loading - Leakage Isolation of Mixed-Signal Devices at Operating Modes - Method for Measuring Package to Board Interconnection Shear Strength for Area Array, Fine Pitch Packages - Picosecond Imaging Circuit Analysis of Leakage Currents in CMOS Circuits - Scanning SQUID Microscopy for Die Level Fault Isolation - A Successful Failure Localization Approach for Defect Identification on High Resistance Interconnects - Backside FIB Device Modifications Through the BOX Layer of an SOI Device - Coax"

"Contents :- Session 1: Advanced Techniques - Scanning Magnetoresistive Microscopy for Die-Level Sub-Micron Current Density Mapping - High Resolution Current Imaging by Direct Magnetic Field Sensing - Fault Isolation of High Resistance Defects using Comparative Magnetic Field Imaging - High Resolution Backside Thermography using a Numerical Aperture Increasing Lens - Session 2: Optical Techniques - Study of Critical Factors Determining Latchup Sensitivity of ICs using Emission Microscopy - New Applications of Thermal Laser Signal Injection Microscopy (T-LSIM) - PC Card Based Optical Probing of Advanced Graphics Processor using Time Resolved Emission - Time-Resolved Optical Measurements from 0.13μm CMOS Technology Microprocessor using a Superconducting Single-Photon Detector - IC Diagnostic with Time Resolved Photon Emission and CAD Auto-channeling - Session 3: Package Level Analysis 1 - 3D X-ray Computed Tomography (CT) for Electronic Packages - High-Angle Electron Microscopy Technique for Analysis of Thin Film Contamination on IC Package Exteriors - Solder Bump Defects in Ceramic Flip Chip Packages and Their Acoustic Signatures. - Copper Bond over Active Circuit (BOAC) and Copper over Anything (COA) Failure Analysis - Investigation of Bond-pad Related Inter-metal Dielectric Crack - Session 4: Sample Preparation 1 - Enhanced SEM Doping Contrast - Interconnect and Gate Level Delayering Techniques for Cu/Low k Technology Failure Analysis - Backside Deprocessing of CMOS SOI Devices for Physical Defect and Failure Analysis - A Novel Approach to Front-side Deprocessing for Thinned Die after Backside Failure Isolation - Session 5: System Level Analysis - Dynamic Infrared System Level Fault Isolation - X-ray Laminography Benchmarking and Failure Analysis of Solder Joint Interfaces - XRF Correlation of Board Reseats due to Intermittent Failures from the use of Thin Gold Plating finish on the Contact Fingers - Session 6: Metrology and Materials Analysis 1 - Deal Time SEM Imaging of FIB Milling Processes for Extended Accuracy on TEM Samples for EFTEM Analysis - A Method for Exact Determination of Dram Deep Trench Surface Area - A Review of TEM Observations of Failures of the Memory Cell in a Deep Trench Capacitor DRAM - The Effect of Tem Specimen Preparation Method on Ultra-thin Gate Dielectric Analysis - Forward Scattered Scanning Electron Microscopy for Semiconductor Metrology and Failure Analysis - Session 7: Failure Analysis Process - Contributions of a Formal Analysis Metaprocess to Breakthrough Failure Analysis Results - SRAM Failure Analysis Strategy - VLSI Design for Functional Failure Analysis in the < 90 nm and Flip-chip era - Identification of an IDDQ Failure Mechanism Using a Variety of Front and Backside Analytical Techniques - Novel Application of Transmission Electron Microscopy and Scanning Capacitance Microscopy for Defect Root Cause Identification and Yield Enhancement - Session 8: Metrology and Materials Analysis 2 - Contact Failure due to Particulate Defect in a 0.13 μm CMOS Process - Microhardness Testing on Via Fill Material for Via In Pad Technology - Application of ToF-SIMS to Airborne Organic Contamination Analysis - Session 9: Test 1 - Yield-Modeling and Test Oriented Taxonomy of IC Structure Deformations - Analysis of IC Manufacturing Process Deformations: An Automated Approach Using SRAM Bit Fail Maps - Electrical Failure Analysis and Characterization of Leakage Paths Leading to Single Cell Failures in 128Mbit SDRAMs - Session 10: Poster - A Study on Fluorine-Induced Corrosion on Microchip Aluminum Bondpads - Advanced Process Defect Detection by Using Dynamic Bias Condition and MCT Camera - Via Chain Failure Analysis Using a Combination of E-Beam and Optical Beam Techniques - ESD Failure Signature Differences in the Devices Core Logic and Protection Structures -- A Case Study - ESD: Correlation between Electrical Signature and Failure Modes - Semi-Automated Cross-Section Process for Complti-Face Perimeter Samples - FIB Micro-pillar sampling of Si devices and its 3D observation - Recent Developments in Automated Sample Preparation for FESEM - Wet Delineation of SEM Samples having Cu Interconnects - An Evolution in Plastic Decapsulation Process Improvement - Near IR Continuous Wavelength Spectroscopy of Photon Emissions from Semiconductor Devices - Defect Isolation and Characterization in Contacts by Using Primary Voltage Adjustment"

"Contents :- Microscopy at the Nanoscale - Polarization Difference Probing: A New Phase Detection Scheme for Laser Voltage Probing - Spray Cooling for Time Resolved Emission Measurements of ICs - A Novel Technique for Detecting High Resistance Fault Using Electroplating - Magnetic Current Imaging Techniques: Comparative Case Studies - Electrical Characterization of sub-30nm Gatelength Soi Mosfets - Combination of SCM/SSRM Analysis and Nanoprobing Technique for Soft Single Bit Failure Analysis - Current Image Atomic Force Microscopy (CI-AFM) Combined with Atomic Force Probing (AFP) for Location and Characterization of Advanced Technology Node. - Towards High Accuracy Fault Diagnosis of Digital Circuits - Broken Scan Chain Diagnostics based on Time-Integrated and Time-Dependent Emission Measurements - Hardware Results Demonstrating Defect Localization Using Power Supply Signal Measurements - Scanning SQUID Microscopy for New Package Technologies - Failure Analysis of Short Faults on Advanced Wire-bond and Flip-chip Packages with Scanning SQUID Microscopy - A Novel Approach to Identifying and Validating Electrical Leakage in Printed Circuit Boards through Magnetic Current Imaging - Extracting Acoustic signatures of Solder Bump Defects using Wavelet Power Spectra and their Classification using Normalized Cross- Correlation. - A Novel X-ray Microtomography System with High Resolution and Throughput For Non-Destructive 3D Imaging of Advanced Packages - Fault Isolation of Large Nets Using Bridging Fault Analysis - Cavity Up and Stack Die Backside Failure Analysis for Thin Die and High Pin Count Devices - Investigation of Substrate Dislocation Induced Bit Line Soft Failure - Overcoming Environmentally Induced Probe Drift for Sub-300nm Fault Isolation - Dislocation Induced Leakage of p+-Implanted ESD Test Macros in 90nm Technology - A Purpose-Driven Decision-Based Methodology for Debug and Failure Analysis - Improved Electrical Failure Analysis / Fault Isolation Tool Development on Server Motherboard Platforms based on Historic Failure Modes - Intel® Component Diagnostic Technology: Tools and Education for Intel Component Defect Reduction - Capacity Management Solutions - A Novel Approach for Enhancing Critical FIB Imaging for Failure Analysis and Circuit Edit Applications - Contacting Silicon with FIB for Backside Circuit Edit - IC Specification Improvement Through Direct Passive Component Modification in the FIB - FIB Chip Repair: Improving Success by Controlling Beam-Induced Damage and Thermal / Mechanical Stress - Precise Fail site Isolation using a combination of Global, Software and Tester based Isolation Techniques - Optimised Probing Flow for High Speed Fault Localization - Diagnostic Fault Simulation for the Failure Analyst - Diagnosing DACS (Defects That Affect Scan Chain and System Logic) - Timing Analysis of a Microprocessor PLL using High Quantum Efficiency Superconducting Single Photon Detector (SSPD) - Analysis of 0.13 um CMOS Technology Using Time Resolved Light Emission - Photon Emission Microscopy in 90 nm CMOS Technologies - Quantifying the Work of Adhesion Between an AFM Cantilever Tip and MEMS Test Structures After Packaging - Reliability of Polycrystalline MEMS : Prediction of the Debugging-time - Failure Analysis of Electrothermal Actuators Subjected to Electrical Overstress (EOS) and Electrostatic Discharge (ESD) - Detecting the 10 Angstroms that Changes MEMS Performance - Scanning Electron Microscope Induced Electrical Breakdown of Tungsten Windows in Integrated Circuit Processing - The Effect Temperature and Strain Rate on Selected Lead Free Solder Alloys - Semiconductor Inter-Material Analysis using a FIB Sample Preparation Method and Auger Depth Profiling - Identification and Characterization of Ultra-thin (<100 nm) Flakes Using a Combination of Face-lapping, High Energy (10 kV) SEM Imaging, and TEM - Materials Characterization of Lead Free Compositions for Minimum Temperature SMT Processes at the SLI-Second Level Interconnect Solder Joint - Measurement of Solder Joint Strength and its Dependence on Thermal Aging in Freestanding and Board-Mounted Packages Using a Laser Spallation Technique - A Methodology for Characterizing System-Level ESD Sensitivity - Design and Process Related Failure Detection with Reliability Testing Incorporating Varying Power Sequencing and Slew Rate - A Study of Power Plane Shapes, Their Contribution to Inter-Planar Electric Field Intensities, and Pre-Preg Breakdown - Characterization of VCSEL-array Degradation Induced by Elevated Temperature and Humidity - FiberQA-AVIT System "

"Control from MEMS to atoms illustrates the use of control and control systems as an essential part of functioning integrated systems. The book is organized according to the dimensional scale of the problem, starting with micro-scale systems and ending with atomic-scale systems. Similar to macro-scale machines and processes, control systems can play a major role in improving the performance of micro- and nano-scale systems and in enabling new capabilities that would otherwise not be possible. However, the majority of problems at these scales present many new challenges that go beyond the current state-of-the-art in control engineering. This is a result of the multidisciplinary nature of micro/nanotechnology, which requires the merging of control engineering with physics, biology and chemistry."