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"Indonesia menduduki peringkat sebagai negara penghasil e-waste tertinggi di Asia Tenggara. Berdasarkan hasil survei Badan Pusat Statistika, Jakarta merupakan kota dengan pengguna internet terbanyak di Indonesia. Dalam menggunakan internet, pengguna harus memiliki produk elektronik seperti handphone, laptop dan komputer. Penumpukkan limbah elektronik didorong oleh penurunan siklus hidup produk elektronik tanpa adanya pengelolaan untuk produk elektronik yang telah usang. Pertumbuhan limbah elektronik di Jakarta disertai dengan rendahnya jumlah limbah elektronik yang terolah dibandingkan dengan jumlah limbah elektronik yang terkumpul. Selain itu faktor yang menyebabkan pertumbuhan limbah elektronik di Jakarta adalah kepadatan penduduknya. Salah satu proses penting dalam pengelolaan limbah elektronik adalah proses pembongkaran. Namun, proses pembongkaran yang dilakukan oleh sektor informal umumnya tidak memiliki prosedur kerja yang aman. Zat berbahaya yang terkandung dalam limbah elektronik berpotensi mencemari lingkungan dan kesehatan di sekitar lokasi pembongkaran jika proses pembongkaran tidak dilakukan dengan prosedur yang aman. Oleh karena itu, perlu dirancang fasilitas pembongkaran yang dapat menjangkau berbagai daerah dengan tetap mempertimbangkan dampaknya terhadap kesehatan dan lingkungan. Tujuan dari penelitian ini adalah untuk merancang fasilitas mobile dismantling limbah elektronik yang dapat menjangkau berbagai daerah dengan mempertimbangkan dampak kesehatan dan lingkungan dalam pengoperasiannya. Penelitian ini menghasilkan rancang bangun fasilitas pembongkaran limbah elektronik yang dirancang dengan menggunakan Systematic Layout Planning. Kajian ini mempertimbangkan dampak kesehatan dan lingkungan, khususnya bagi manusia dan lingkungan sekitar area pembongkaran dengan menggunakan metode Hazard Identification Risk Assessment & Control.

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Indonesia was ranked as the highest e-waste-producing country in Southeast Asia. According to the survey's findings, Jakarta is the city with the most internet users. In order to use the internet, users must have electronic products like handphones, laptop and computer. The rapid changes in the field of information and communication technology, along with a downward price trend has led to a decrease in life cycle of electronic products. The collection of electronic waste can be driven by the decrease of electronic product's life cycle without a proper management for obsolete electronic products. The growth of e-waste in Jakarta is accompanied by less processed e-waste compared with the e-waste collected. One of the factors contributing to the rise of e-waste in Jakarta is its population density. The important process for managing electronic waste is the dismantling process. However, the dismantling process carried out by the informal sector generally does not have safe work procedures. Hazardous substances contained in electronic waste have a potential to contaminate the environment and health around the dismantling location if the dismantling process is not carried out with safe procedures. Therefore, it is necessary to design dismantling facilities that can reach various areas while still considering the impact on health and the environment. The purpose of this research is to design a mobile dismantling facility that can reach various areas by considering the health and environmental impacts from its operation. This research resulted a design of electronic waste dismantling facility using Systematic Layout Planning to operate on a mobile basis so that it can reach various areas in its operation. This study considers the health and environmental impacts, especially for humans and the environment around the dismantling area using Hazard Identification Risk Assessment & Control method."

"Contents :- A Comparitive Study of Electron and Ion Beam Induced Charge Imaging Techniques in CMOS Failure Analysis - Infrared Light Emission From Semiconductor Devices - The Use of Near-Field Scanning Optical Microscopy for Failure Analysis of ULSI Circuits - Golden Devices II: Alchemy in the 0.35 um Era - Focused Ion Beam Assisted Circuit Debug of a Video Graphics Chip - Two Unique Case Studies Performed With Photoemission Microscopy (PEM) - Application of Photoemission Microscopy and Focused Ion Beam Microsurgery to an Investigation of Latchup - Localizing Heat-Generating Defects Using Fluorescent Microthermal Imaging - A User-Friendly System for Fluorescent Microthermal Imaging and Light Emission Microscopy - Fast, Clean and Low Damage Deprocessing Using Inductively Coupled and RIE Plasmas - X-Ray Microfocus Radioscopy and Computed Tomography for Failure Analysis - Low Resistivity FIB Depositions Within High Aspect Ratio Holes - Grains Observation Using FIB Anisotropic Etch Followed by AFM Imaging - Cross-Sectional Specimen Preparation of Fragile Failure Location in Thin-Film Transistors Using Focused Ion Beam Etching and Transmission Electron Microscope - Low Acceleration Voltage EBIC Using FESEM and Application to Cross- Sectional Junction Evaluation - Contamination Diagnosis Using Contamination-Defect-Fault (CDF) Simulation - FLOSPAT: Fault Localization by Sensitized Path Transformation - Fault Verification Simulation for Light-Emission Microscopy and Liquid-Crystal Analysis - Fault Diagnosis on the TMS320C80 (MVP) Using FastScanTM - Modeling IC Defects Using Circuit Simulation Software - Characterization of Unfilled Tungsten Plugs on a 0.35 um CMOS Multilevel Metallization Process - Failure Analysis of a Half-Micron CMOS IC Technology - Burn-in Failure Analysis of 0.5 um 1 MB SRAM: Barrier Glue Layer Cracks and Tungsten Plug - The Application of Novel Failure Analysis Techniques and Defect Modeling in Eliminating Short Poly End-Cap Problem in Submicron CMOS Devices - Case Study: Unique Stress Induced Gate Oxide Defects in a CMOS Analog/Digital Device Revealed by Backside Silicon Removal - Risk Assessment in Signature Analysis - Signature Analysis: Statistical Models and Their Application to FA - A Signature Analysis Method for IC Failure Analysis - TEM Sample Preparation Using A Focused Ion Beam and A Probe Manipulator - Pin-Point Transmission Electron Microscopic Analysis Applied to Off-Leakage Failures of a Bipolar Transistor in 0.5 um BiCMOS Devices - TEM Cross-Sectional Analysis of ESD Induced Damage in Input Protection Circuitry - A Study of Measurement Methods for Detecting Voiding and Delamination of Die Attach Materials in Power Semiconductor Devices - Failure Analysis of the Die-Attach in a Metal-Type Package - Charge Diffusion and Reciprocity Theorems: A Direct Approach to EBIC of Ridge Laser Diodes - Characterization and Elimination of Forward Snapback Defects in GaAs Light Emitting Diodes - Temperature Dependence of Quiescent Currents as a Defect Prognosticator and Evaluation Tool - Contactless Testing of Pulse Propagation in IC's-A Comparison Between OBIC and Captive-Coupling Detection Techniques - Electron-Beam Analysis of the Turn-On Speed of Grounded-Gate NMOS ESD Protection Transistors During Charged Device-Model Stress Pulses - Contactless Function Test of Integrated Circuits on the Wafer - Package Related Failure Mechanisms in Plastic BGA Packages Used for ASIC Devices - Failure Analysis of Flip-Chip Interconnections Through Acoustic Microscopy - Signature Analysis of Package Delamination Using Scanning Acoustic Microscope - A Case Study of Post De-Tape Cleans on Mold Compound Adhesion - Spatial Evaluation of Resolution in a Scanning Ultrasonic Microscope. Microassembling Technologies Characterization: Differences Between A-Scan and C-Scan Analysis Modes - Macro and Micro Thermal Model of an Elevated Temperature Dielectric Breakdown in Printed Circuit Boards - A Review of Wet Etch Formulas for Silicon Semiconductor Failure Analysis 301 Carbon Coating for Electron Beam Testing and Focus Ion Beam Reconfiguration - A Technique for Achieving Precision Cross Sections of Released Surface Micromachined Structures - The Study of ESD Destructive Mechanism for PN-Junction - Interconnect Failure Dependence on Crystallographic Structure - Dielectric Breakdown in Printed Circuit Boards at Elevated Temperatures - Mechanism Study of Contact Corrosion in Unpatterned Metal Wafer - TPLY for Yield Improvement - A New Robust Backside Flip-Chip Probing Methodology "