Hasil Pencarian  ::  Simpan CSV :: Kembali

"This book presents a new FPGA architecture known as tree-based FPGA architecture, due to its hierarchical nature. This type of architecture has been relatively unexplored despite their better performance and predictable routing behavior, as compared to mesh-based FPGA architectures. In this book, we explore and optimize the tree-based architecture and we evaluate it by comparing it to equivalent mesh-based FPGA architectures."

"Heterogeneous embedded systems, signal representations and different abstraction levels, architectures and components based on hardware and software, in all the main phases of design (modeling, validation with multiple models of computation, synthesis and optimization). It concentrates on the specific issues at the interfaces, and is divided into two main parts. The first part examines mainly theoretical issues and focuses on the modeling, validation and design techniques themselves. The second part illustrates the use of these methods in various design contexts at the forefront of new technology and architectural developments."

"The book discusses the latest developments and outlines future trends in the fields of microelectronics, electromagnetics and telecommunication. It contains original research works presented at the International Conference on Microelectronics, Electromagnetics and Telecommunication (ICMEET 2018), organised by GVP College of Engineering (A), Andhra Pradesh, India. The respective papers were written by scientists, research scholars and practitioners from leading universities, engineering colleges and R&D institutes from all over the world, and share the latest breakthroughs in and promising solutions to the most important issues facing todays society."

"This book is dedicated to the analysis of parametric amplification with special emphasis on the MOS discrete-time implementation. This implementation is demonstrated by the presentation of several circuits where the MOS parametric amplifier cell is used, small gain amplifier, comparator with embedded pre-amplification, discrete-time mixer/IIR-Filter, and analog-to-digital converter (ADC). Experimental results are shown to validate the overall design technique."

"Divais SET dapat digunakan untuk banyak aplikasi seperti single electron switching, single photon detector, single electron detector, quantum bit memory, dll. Untuk aplikasi seperti quantum bit memory, diperlukan dua buah quantum dot (QD) yang disusun secara paralel. Pada thesis ini, dua buah SET yang disusun secara paralel disimulasikan dengan software SIMON 2.0 untuk mendapatkan parameter-parameter yang diperlukan guna mengontrol perpindahan elektron antar QD. Dari hasil simulasi, didapatkan bahwa dua buah SET yang disusun secara paralel bertindak sebagai dua buah SET yang independen pada saat junction capacitance antar QD bernilai di atas 5×10–18 F. Perpindahan elektron antar QD terjadi apabila terdapat perbedaan potensial pada dua QD yang melebihi suatu nilai minimum. Nilai minimum tersebut dipengaruhi oleh resistansi dan kapasitansi junction capacitance. Semakin besar resistansi, nilai minimum perbedaan potensial yang diperlukan akan semakin membesar sedangkan apabila kapasitansi semakin besar, nilai minimum perbedaan potensial yang diperlukan akan semakin mengecil.

---

SET devices can be used in many applications, such as single electron switching, single photon detector, single electron detector, quantum bit memory, etc. For applications such as quantum bit memory, two quantum dots (QDs) in parallel position are required. In this thesis, two SETs in parallel configuration are simulated with SIMON 2.0 software in order to obtain parameters which are needed to control the interdot electron movement. From the results of the simulation, it is obtained that two SETs in parallel configuration will act as two independent SETs when the interdot junction capacitance is above 5×10–18 F. The interdot electron movement occurs when a potential difference exist between the two QDs. The same potential difference must surpass the required minimum value which is influenced by the interdot resistance and capacitance. The bigger the resistance, the required minimum value of potential difference will be increased while the bigger the capacitance, the required minimum value of potential difference will be decreased."

"This book cover a key subject for the successful realization of DSP algorithms for communications, multimedia, and healthcare applications. The book addresses the need for DSP architecture design that maps advanced DSP algorithms to hardware in the most power- and area-efficient way. The key feature of this text is a design methodology based on a high-level design model that leads to hardware implementation with minimum power and area. The methodology includes algorithm-level considerations such as automated word-length reduction and intrinsic data properties that can be leveraged to reduce hardware complexity. From a high-level data-flow graph model, an architecture exploration methodology based on linear programming is used to create an array of architectural solutions tailored to the underlying hardware technology."